Senior NoC Research Engineer – Network-on-Chip

• Explore and evaluate NoC topologies, router and switch designs, arbitration, flow control, QoS and congestion control
• Build and maintain architectural models and simulations using SST, gem5 or custom cycle-level and analytical models
• Develop traffic generators reflecting real ML workloads, including collective communication, tensor parallelism and memory traffic
• Analyse power, performance and area (PPA) trade-offs and back recommendations with quantitative evidence
• Ensure deadlock- and livelock-free designs through analysis, formal methods or simulation
• Investigate adaptive routing strategies and topology options
• Translate complex protocol and IP specifications such as AXI, CHI and APB into clear design requirements
• Evaluate third-party interconnect IP and support build-versus-buy decisions
• Assess RDMA concepts and chip-to-chip interfaces for accelerator data movement at system scale
• Present findings and recommendations to architecture and leadership teams
• Contribute to publications and patents in on-chip networks and data movement for ML
• Report to the CTO and collaborate with chip architecture, hardware and software teams

• PhD, or Master's with equivalent research experience, in Electrical Engineering, Computer Engineering, Computer Science or a related field
• Senior-level track record in NoC or interconnect architecture, in industry or applied research
• Strong background in on-chip interconnect and traffic management: NoC topologies, routers and switches, arbitration, flow control, QoS and congestion control
• Good understanding of ML workloads and accelerator architectures, including collective communication, tensor parallelism and memory traffic
• Working knowledge of on-chip protocols such as AXI, CHI or AHB
• Understanding of RDMA concepts and transports (InfiniBand, RoCE), including queue pairs, memory registration and zero-copy transfers
• Experience reasoning about PPA trade-offs with quantitative evidence
• Hands-on architectural modelling and simulation (SST, gem5 or own models), with strong Python and C++
• Ability to read complex protocol and IP specifications and turn them into clear design requirements
• Experience with deadlock and livelock avoidance, adaptive routing or topology exploration
• Clear written and verbal communication in English, and a proactive, collaborative approach to open-ended problems

• 30 days annual vacation
• Up to 2 weeks of work abroad
• Work on cutting-edge sparse computing technology
• High-impact role with direct influence on the architecture of SpiNNext
• Collaborative team culture with experienced engineers from academia and industry
• Equity participation in a growing deep-tech company