Design Verification Engineer

• Own verification of IPs from the RTL level to emulation, resulting in fully functional and performant products
• Establish functional and performance benchmarks with help from Senior Engineers
• Actively participate in discussions about the definition, execution, and continuous improvement of a robust design verification methodology and tools flow across different verification platforms

• Sound knowledge of System Verilog
• Good experience in Constrained Random and Coverage Driven Verification
• Experience in creating UVC components or sequences
• Basic knowledge of at least one of: AHB/AXI, PCIe/CXL, USB, DDR, serial protocols, processor verification
• Comfort updating the existing verification environment for feature updates
• Good knowledge of Perl, TCL, or Python scripting
• Experienced Professionals experience level

• Health insurance from the first days, regardless of the probationary period
• Christmas holidays from December 25 to December 31
• Psychological counseling provided by the Veteran Hub
• Internal policy making the company friendly to military and veterans
• Cooperation with Superhumans center and Veteran HUB