Lead / Principal Engineer, Ethernet Scale - Up

• Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics
• Lead development of high-performance Ethernet subsystem microarchitectures, including RDMA, packet processing, network offload, traffic management, congestion control, and reliability mechanisms
• Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production
• Optimize performance, latency, scalability, power, and reliability for demanding AI and HPC workloads
• Collaborate across hardware, firmware, software, and system teams to deliver AI networking solutions
• Serve as a company-wide technical leader influencing product strategy, roadmap, and architectural direction
• Define and validate Ethernet Scale-Up Networking architecture for next-generation HPC and rack-scale AI systems
• Deliver production-quality Ethernet subsystem microarchitecture on schedule
• Align and unblock cross-functional teams across hardware, firmware, software, and systems

• 15+ years of ASIC/SoC architecture and design experience
• Proven track record delivering networking, NIC, switch, DPU, accelerator interconnect, or high-speed connectivity silicon
• Deep expertise in SystemVerilog/RTL design and high-performance datapath architecture
• Strong knowledge of Ethernet, RDMA, traffic management, congestion control, and scalable fabric architectures
• Experience across the full ASIC lifecycle, from architecture to production silicon
• Ultra Ethernet, UALink, RoCEv2, InfiniBand, PCIe Gen6/Gen7, UCIe, CXL, AI/HPC interconnects, and collective communication acceleration
• Experience with 400G/800G/1.6T Ethernet systems
• Experience with high-speed SerDes and advanced networking architectures

• Remote-friendly work arrangement
• Opportunity to work with a global team
• Opportunity to work on consequential AI/HPC silicon infrastructure
• Ownership of technical roadmap and architectural direction
• High-impact role with company-wide technical influence