Senior DFT Engineer

• Own Design-for-Test on customer SoCs end-to-end
• Define and implement DFT architecture
• Perform scan and ATPG implementation
• Implement memory BIST and boundary scan
• Validate test patterns
• Conduct DFT DRC analysis and coverage debugging
• Set up and run gate-level simulations
• Perform formal equivalence checking
• Automate DFT flows using scripting
• Support production test hand-off
• Work on customer SoCs for an ASIC and COT design and turnkey manufacturing services company
• Contribute across the product lifecycle from architecture and RTL-to-GDSII implementation through silicon, package, and test

• BSc in Electrical Engineering from a recognized university
• Minimum 3 years of hands-on DFT experience — must; senior-level profiles preferred
• Experience with scan, ATPG, at-speed test, memory BIST, and I/O DFT methodologies
• Experience with scan insertion and ATPG for stuck-at, transition-delay, bridging, and IDDQ fault models; test-coverage improvement
• Experience with DFT DRC analysis and coverage debugging using Synopsys DFT Compiler, TestMAX (TetraMAX), SpyGlass DFT, or equivalent Siemens (Mentor) Tessent tools
• Experience with Tessent MBIST
• Strong knowledge of JTAG IEEE 1149.1, IEEE 1149.6, and IEEE 1500 (formerly P1500)
• Hands-on design and implementation of DFT features
• End-to-end DFT flow ownership from concept through tape-out to production
• Gate-level simulation setup and execution for pattern validation
• Formal equivalence checking
• Perl, Tcl, and UNIX scripting for flow automation
• Broader Siemens Tessent experience (ScanPro / TestKompress, LBIST) beyond MBIST preferred
• Advanced-node experience (7nm and below) preferred
• Python for flow automation preferred